MIPS: Fix invalidate_dcache_range to operate on L1 Dcache

Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.

Signed-off-by: Paul Burton <[email protected]>
Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 5f520c069f6205ea977ea96c383933455ea0dc89..db81953f86c5486bd1730fed99ac72a5b52f7401 100644 (file)
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        if (start_addr == stop)
                return;
 
-       cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
+       cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
 }